The escalating requirements for increased densification and performance in ultra-large scale integration semiconductor wiring require responsive changes in interconnection technology. High density demands for ultra-large scale integration semiconductor wiring require planarized conductive patterns comprising contacts/vias, conductive lines and/or interwiring spacings with a maximum dimension of less than about 0.35 microns.
A traditional method for forming interconnection structures comprises the use of a subtractive etching or etch back step as the primary metal patterning technique. Such a traditional method comprises depositing a dielectric layer on a semiconductor substrate, typically monocrystalline silicon, and forming conductive contacts/vias in the insulating layer. A metal layer, such as tungsten, aluminum, or an alloy thereof, is deposited on the insulating layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to the desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern. A dielectric layer is then applied to the resulting conductive pattern filling in the interwiring spaces between the conductive lines.
There are various problems attendant upon the traditional etch back technique. For example, it is difficult to form an adequately planarized layer subsequent to filling in the interwiring spacings between the conductive lines, as by conventional etching and chemical-mechanical polishing (CMP) planarization techniques, particularly with reduced interwiring spacings. In addition, the traditional etch back technique often results in the generation of voids in the filled-in interwiring spacings. Additional difficulties include trapping of impurities of volatile materials in the interwiring spacings thereby exposing the semiconductor device to potential damage. Moreover, it is difficult to provide adequate step courage using the traditional etch back technique.
Prior attempts to overcome the disadvantages of the traditional etch back technique involve the application of damascene to form a conductive pattern. Damascene is an art which has been employed for centuries in the fabrication of jewelry, and has recently been adapted for application in the semiconductor industry. Damascene basically involves the formation of an opening for a contact or via, or a trench, typically a substantially horizontally extending trench, which is filled with a metal. Thus, damascene differs from the traditional etch back technique of providing an interconnection structure by forming a pattern of trenches in a dielectric layer, which trenches are filled in with metal to form the conductive pattern followed by planarization vis-a-vis the traditional etch back technique of depositing a metal layer, forming a conductive pattern with interwiring spacings, and filling in the interwiring spacings with dielectric material. Double damascene techniques can be utilized to form both a contact/via and trench simultaneously filled with a conductive material.
As the design requirements for interconnection patterns become more severe in requiring maximum dimensions less than about 0.35 microns, particularly less than about 0.25 microns, the ability of conventional methodology to meet such demands with acceptable accuracy becomes increasingly more difficult. A limitation on achieving such fine dimensions resides in the inability of conventional photolithographic and etching techniques to satisfy the accuracy requirements for such fine feature sizes. Conventionally, in providing feature sizes having a small dimension, such as about 0.30 to about 0.40 microns or greater, I-line photolithography is employed. As the maximum dimension is reduced, e.g., to below about 0.30 microns, such as less than about 0.25 microns, it is necessary to resort to shorter wavelengths, such as deep ultra-violet light. However, it is very difficult to form fine line patterns or through-holes with a maximum dimension of about 0.25 microns or less with any reasonable degree of accuracy, consistency and efficiency, and to produce a controlled sidewall by a simple etching process.
In co-pending application Ser. No. 08/528,279 filed on Sep. 14, 1995, now Ser. No. 08/974,687 a method is disclosed for forming sub-micron contacts/vias and trenches in a dielectric layer, which method comprises forming an opening having an initial dimension and reducing the initial dimension by forming a dielectric sidewall in the opening to reduce the initial dimension to a smaller final dimension. The entire disclosure of co-pending application Ser. No. 08/528,279 now Ser. No. 08/974,687 is incorporated herein by reference. Japanese Patent Document 63-253647, Lee, U.S. Pat. No. 4,641,420 and UK Patent Application GB 2,251,722A disclose methods of forming contacts/vias in dielectric layers having a sidewall spacer therein.
There exists a need for a cost effective, simplified method of accurately forming interconnection structures with ultra-fine feature dimensions, e.g., less than about 0.25 microns. There also exists a need for a method of forming such ultra fine features using conventional photolithographic equipment without resort to e-beam or X-ray lithographic techniques.